ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 51

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5
5.6
5.7
5.8
8077H–AVR–12/09
Addressing
Priority Between Channels
Double Buffering
Transfer Buffers
By default, a trigger starts a block transfer operation. The transfer continues until one block is
transferred. When the block is transferred, the channel will wait for the next trigger to arrive
before it start transferring the next block. It is possible to select the trigger to start a burst transfer
instead of a block transfer. This is called a single shot transfer. A new trigger will then start a new
burst transfer. When repeat mode is enabled, the start of transfer of the next block does not
require a transfer trigger. It will start as soon as the previous block is done.
If the trigger source generates a transfer request during an ongoing transfer this will be kept
pending, and the transfer can start when the ongoing one is done. Only one pending transfer
can be kept, so if the trigger source generates more transfer requests when one is already pend-
ing, these will be lost.
The source and destination address for a DMA transfer can either be static, incremental or dec-
remental with individual selections for source and destination. When address increment or
decrement is used, the default behaviour is to update the address after each access. The origi-
nal source and destination address is stored by the DMA controller, so the source and
destination addresses can be individually configured to be reloaded at the following points:
If several channels request data transfer at the same time a priority scheme is available to deter-
mine which channel is allowed to transfer data. Application software can decide whether one or
more channels should have a fixed priority or if a round robin scheme should be used. A round
robin scheme means that the channel that last transferred data will have the lowest priority.
To allow for continuous transfer, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa. This is called double buffering. When a
transmission is completed for the first channel, the second channel is enabled. When a request
is detected on the second channel, the transfer starts and when this is completed the first chan-
nel is enabled again.
Each DMA channel has an internal transfer buffer that is used for 2, 4 and 8 byte burst transfers.
When a transfer is triggered, a DMA channel will wait until the transfer buffer contains two bytes
before the transfer starts. For 4 or 8 byte transfer, any remaining bytes is transferred as soon as
they are ready for a DMA channel. The buffer is used to reduce the time the DMA controller
occupy the bus. When the DMA controller or a DMA channel is disabled from software, any
remaining bytes in the buffer will be transferred before the DMA controller or DMA channel is
disabled. This ensures that the source and destination address registers are kept synchronized.
• End of each burst transfer
• End of each block transfer
• End of transaction
• Never reload
XMEGA A
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