ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 159

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.7.4
14.7.5
14.8
8077H–AVR–12/09
Compare Channel
32-bit Input Capture
Capture Overflow
Figure 14-11. Pulse-width capture of external signal.
Two Timer/Counters can be used together to enable true 32-bit Input Capture. In a typical 32-bit
Input Capture setup the overflow event of the least significant timer is connected via the Event
System and used as clock input for the most significant timer.
Since all events are pipelined, the most significant timer will be updated one peripheral clock
period after an overflow occurs for the least significant timer. To compensate for this delay the
capture event for the most significant timer must be equally delayed by setting the Event Delay
bit for this timer.
The Timer/Counter can detect buffer overflow on any of the Input Capture Channels. In the case
where both the Buffer Valid flag and Capture Interrupt Flag are set, and a new capture event is
detected there is nowhere to store the new time-stamp. If a buffer overflow is detected the new
value is rejected, the Error Interrupt Flag is set and the optional interrupt is generated.
Each compare channel continuously compares the counter value (CNT) with the CCx register. If
CNT equals CCx the comparator signals a match. The match will set the CC channel's interrupt
flag at the next timer clock cycle, and the event and optional interrupt is generated.
The compare buffer register provides double buffer capability equivalent to the period buffer.
The double buffering synchronizes the update of the CCx register with the buffer value to either
the TOP or BOTTOM of the counting sequence according to the UPDATE condition signal from
the Timer/Counter control logic. The synchronization prevents the occurrence of odd-length,
non-symmetrical PWM/FRQ pulses, thereby making the output glitch-free.
external signal
events
CNT
MAX
BOT
Pulsewitdh (t
p
)
XMEGA A
"capture"
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