ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 62

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.14.9
5.14.10
5.14.11
5.14.12
8077H–AVR–12/09
SRCADDR1 - DMA Channel Source Address 1
SRCADDR0 - DMA Channel Source Address 0
DESTADDR2 - DMA Channel Destination Address 2
DESTADDR1 - DMA Channel Destination Address 1
• Bit 7:0 - SRCADDR[23:16]: DMA Channel Source Address 2
These bits hold byte 2 of the 24-bits source address.
• Bit 7:0 - SRCADDR[15:8]: DMA Channel Source Address 1
These bits hold byte 1 of the 24-bits source address.
• Bit 7:0 - SRCADDR[7:0]: DMA Channel Source Address 0
These bits hold byte 0 of the 24-bits source address.
DESTADDR0, DESTADDR1 and DESTADDR2 represents the 24-bit value DESTADDR, which
is the DMA channel destination address. DESTADDR2 holds the most significant byte in the reg-
ister. DESTADDR may be automatically incremented or decremented based on settings in the
DESTDIR bits in
Reading and writing 24-bit values require special attention, for details refer to
”Accessing 24- and 32-bit Registers” on page
• Bit 7:0 - DESTADDR[23:16]: DMA Channel Destination Address 2
These bits hold byte 2 of the 24-bits source address.
Bit
+0x08
Read/Write
Initial Value
Bit
+0x0E
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
Bit
+0x0D
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
”ADDRCTRL - DMA Channel Address Control Register” on page
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
DESTADDR[23:16]
R/W
R/W
R/W
4
0
DESTADDR[15:8]
SRCADDR[15:8]
4
0
4
0
4
0
SRCADDR[7:0]
12.
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Section 3.11.1
57.
DESTADDR2
DESTADDR1
SRCADDR1
SRCADDR0
62