ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 129

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. I/O Ports
13.1
13.2
8077H–AVR–12/09
Features
Overview
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XMEGA has flexible General Purpose I/O (GPIO) Ports. A port consists of up to 8 pins ranging
from pin 0 to 7, where each pin can be configured as input or output with highly configurable
driver and pull settings. The ports also implement several functions including interrupts, synchro-
nous/asynchronous input sensing and asynchronous wake-up signalling.
All functions are individual per pin, but several pins may be configured in a single operation. All
ports have true Read-Modify-Write (RMW) functionality when used as general purpose I/O ports.
The direction of one port pin can be changed without unintentionally changing the direction of
any other pin. The same applies when changing drive value when configured as output, or
enabling/disabling of pull-up or pull-down resistors when configured as input.
Figure 13-1 on page 130
controlling a pin.
Selectable input and output configuration for each pin individually
Flexible pin configuration through dedicated Pin Configuration Register
Synchronous and/or asynchronous input sensing with port interrupts and events
Asynchronous wake-up signalling
Highly configurable output driver and pull settings:
Slew rate control
Flexible pin masking
Configuration of multiple pins in a single operation
Read-Modify-Write (RMW) support
Toggle/clear/set registers for OUT and DIR registers
Clock output on port pin
Event Channel 0 output on port pin 7
Mapping of port registers (virtual ports) into bit accessible I/O memory space
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Totem-pole
Pull-up/-down
Wired-AND
Wired-OR
Bus keeper
Inverted I/O
shows the I/O pin functionality, and the registers that is available for
XMEGA A
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