ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 344

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29. Program and Debug Interface
29.1
29.2
8077H–AVR–12/09
Features
Overview
•
•
•
•
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external program-
ming and on-chip debugging of the device.
The PDI supports high-speed programming of all Non-Volatile Memory (NVM) spaces; Flash,
EEPOM, Fuses, Lockbits and the User Signature Row. This is done by accessing the NVM Con-
troller, and executing NVM Controller commands as described in Memory Programming.
The On-Chip Debug (OCD) system supports fully intrusive operation. During debugging no soft-
ware or hardware resources in the device is used (except for four I/O pins required if JTAG
connection is used). The OCD system has full program flow control, supports unlimited number
of program and data breakpoints and has full access (read/write) to all memories.
Both programming and debugging can be done through two physical interfaces. The primary
interface is the PDI Physical. This is a 2-pin interface using the Reset pin for the clock input
Program and Debug Interface (PDI)
Programming Features
Debugging Features
JTAG Interface
– 2-pin interface for external programming and on-chip debugging
– Uses Reset pin and dedicated Test pin
– Flexible communication protocol
– 8 Flexible instructions.
– Minimal protocol overhead.
– Fast
– Reliable
– Non-Intrusive Operation
– Complete Program Flow Control
– 1 dedicated program address breakpoint or symbolic breakpoint for AVR studio/emulator
– 4 Hardware Breakpoints
– Unlimited Number of User Program Breakpoints
– Uses CPU for Accessing I/O, Data, and Program
– High Speed Operation
– JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
– Programming features as for PDI
– On-chip debug features as for PDI
• No I/O pins required during programming or debugging
• 10 MHz programming clock at 1.8V V
• Built in error detection and handling
• Uses no hardware or software resource
• Symbolic Debugging Support in Hardware
• Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
• No limitation on system clock frequency
CC
XMEGA A
344