ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 90

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.10.5
7.10.6
8077H–AVR–12/09
RC32KCAL - 32 KHz Oscillator Calibration Register
PLLCTRL - PLL Control Register
• Bit 7:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, the XOSCFDIF is set when a
failure is detected. Writing logic one to this location will clear XOSCFDIF. Note that having this
flag set will not stop the fail monitor circuit to request a new interrupt if the external clock sources
are re-enabled and a new failure occurs.
• Bit 0 - XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a Non-Maskable Interrupt will be
issued when the XOSCFDIF is set.
This bit is protected by the Configuration Change Protection mechanism, refer to
”Configuration Change Protection” on page 12
will only be disabled by a reset.
• Bit 7:0 - RC32KCAL[7:0]: 32.768 KHz Internal Oscillator Calibration Register
This register is used to calibrate the Internal 32.768 kHz Oscillator. A factory-calibrated value is
loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency close to 32.768 kHz. The register can also be written from software to cali-
brate the oscillator frequency during normal operation.
• Bit 7:6 - PLLSRC[1:0]: Clock Source
The PLLSRC bits select the input source for the PLL according to
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
R/W
7
x
R/W
7
0
PLLSRC[1:0]
R/W
6
x
R/W
6
0
R/W
5
x
R
5
0
-
R/W
4
RC32KCAL[7:0]
x
R/W
4
0
for details. Once enabled, the failure detection
R/W
3
x
R/W
3
0
PLLFAC[4:0]
R/W
2
x
R/W
2
0
Table 7-7 on page
R/W
1
x
R/W
1
0
XMEGA A
R/W
0
x
R/W
0
0
Section 3.12
91.
RC32KCAL
PLLCTRL
90