DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 70
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 70 of 269
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Table 11-3. E1 Alarm Criteria
V52LNK
ALARM
RDMA
RLOS
RUA1
RRA
RCL
An RLOS condition exists on
power-up prior to initial
synchronization, when a resync
criteria has been met, or when a
manual resync has been initiated
via E1RCR1.0
255 or 2048 consecutive zeros
received as determined by
E1RCR2.0
Bit 3 of non-align frame set to
one for three consecutive
occasions
Fewer than three zeros in two
frames (512 bits)
Bit 6 of time slot 16 in frame 0
has been set for two consecutive
multiframes
Two out of three Sa7 bits are
zero
SET CRITERIA
70 of 269
In 255-bit times, at least 32 ones
are received
Bit 3 of nonalign frame set to
zero for three consecutive
occasions
More than two zeros in two
frames (512 bits)
CLEAR CRITERIA
DS21455/DS21458 Quad T1/E1/J1 Transceivers
G.775/G.962
SPEC.
1.6.1.2
O.162
O.162
G.965
2.1.4
ITU
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