DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 147

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Channel Bit 1 Suppress Enable/Sa8 Bit Enable (RCB1SE ). LSB of the channel. Set to one to stop this bit
from being used when the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa
bits.
Bit 1/Receive Channel Bit 2 Suppress Enable/Sa7 Bit Enable (RCB2SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 2/Receive Channel Bit 3 Suppress Enable/Sa6 Bit Enable (RCB3SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 3/Receive Channel Bit 4 Suppress Enable/Sa5 Bit Enable (RCB4SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 4/Receive Channel Bit 5 Suppress Enable/Sa4 Bit Enable (RCB5SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 5/Receive Channel Bit 6 Suppress Enable (RCB6SE). Set to one to stop this bit from being used.
Bit 6/Receive Channel Bit 7 Suppress Enable (RCB7SE). Set to one to stop this bit from being used.
Bit 7/Receive Channel Bit 8 Suppress Enable (RCB8SE). MSB of the channel. Set to one to stop this bit from being used.
RCB8SE
7
0
RCB7SE
H1RTSBS, H2RTSBS
HDLC # 1 Receive Time Slot Bits/Sa Bits Select
HDLC # 2 Receive Time Slot Bits/Sa Bits Select
96h, A6h
6
0
RCB6SE
5
0
RCB5SE
4
0
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RCB4SE
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
RCB3SE
2
0
RCB2SE
1
0
RCB1SE
0
0