DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 235

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DS21458LDK

Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled)
NOTES:
1) TSYNC is in the output mode (IOCR1.1 = 1).
2) TSYNC is in the input mode (IOCR1.1 = 0).
3) TCHBLK is programmed to block channel 2.
4) Shown is TLINK/TLCLK in the ESF framing mode.
TCHBLK
TCHCLK
TSYNC
TSYNC
TLCLK
TLINK
TSER
TCLK
TSIG
1
2
3
4
LSB
D/B
F
MSB
CHANNEL 1
CHANNEL 1
A
B
C/A
235 of 269
LSB MSB
D/B
DON'T CARE
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CHANNEL 2
CHANNEL 2
A
B
C/A
LSB MSB
D/B

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