DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 265

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DS21458LDK

Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
38.4 Transmit AC Characteristics
AC CHARACTERISTICS–TRANSMIT SIDE
(V
V
TCLK Period
TCLK Pulse Width
TCLKI Period
TCLKI Pulse Width
TSYSCLK Period
TSYSCLK Pulse Width
TSYNC or TSSYNC Setup to TCLK
or TSYSCLK Falling
TSYNC or TSSYNC Pulse Width
TSER, TSIG, TDATA, TLINK,
TPOSI, TNEGI Setup to TCLK,
TSYSCLK, TCLKI Falling
TSER, TSIG, TDATA, TLINK Hold
from TCLK or TSYSCLK, Falling
TPOSI, TNEGI Hold from TCLKI
Falling
TCLK, TCLKI, or TSYSCLK Rise
and Fall Times
Delay TCLKO to TPOSO, TNEGO
Valid
Delay TCLK to TESO Valid
Delay TCLK to TCHBLK, TCHCLK,
TSYNC, TLCLK
Delay TSYSCLK to TCHCLK,
TCHBLK
NOTES:
1) TSYSCLK = 1.544MHz.
2) TSYSCLK = 2.048MHz.
3) TSYSCLK = 4.096MHz.
4) TSYSCLK = 8.192MHz.
5) TSYSCLK = 16.384MHz.
DD
DD
= 3.3V 5%, T
= 3.3V 5%, T
PARAMETER
A
A
= -40°C to +85°C; for DS21455N/DS21458N.) (See
= 0°C to +70°C for DS21455/DS21458;
SYMBOL
t
R
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CH
PW
HD
HD
DD
CP
CL
LH
LL
SU
SU
D1
D2
D3
LP
SP
SP
, t
F
265 of 269
MIN
20
20
20
20
20
20
20
50
20
20
20
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TYP (E1)
488 (E1)
648 (T1)
488 (E1)
648 (T1)
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
648
448
244
122
61
CP
CP
LP
LP
SP
SP
Figure 38-13
MAX
25
50
50
50
22
UNITS
to
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
38-15.)
NOTES
1
2
3
4
5

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