DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 12
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 12 of 269
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2.4 Jitter Attenuator
2.5 Framer/Formatter
32-bit or 128-bit crystal-less jitter attenuator
Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use
Can be placed in either the receive or transmit path or disabled
Limit trip indication
Fully independent transmit and receive functionality
Full receive- and transmit-path transparency
T1 framing formats include D4, ESF, J1-D4, J1-ESF and SLC-96
Japanese J1 support for CRC6 and yellow alarm
E1 framing formats include FAS, CAS, and CRC-4
Detailed alarm- and status-reporting with optional interrupt support
Large path- and line-error counters for:
User-defined Idle Code Generation on a per-channel basis in both transmit and receive paths
Digital milliwatt code generation on the receive path
ANSI T1.403-1998 support
G.965 V5.2 link detect
RAI-CI detection and generation
AIS-CI detection and generation
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating-pattern generators and detectors
RCL, RLOS, RRA, and RAIS alarms interrupt on change of state
Flexible signaling support
Hardware pins to indicate carrier loss and signaling freeze
Automatic RAI generation to ETS 300 011 specifications
Expanded access to Sa and Si bits
Option to extend carrier-loss criteria to a 1ms period as per ETS 300 233
1.544MHz for T1 operation
T1 – BPV, CV, CRC6, and framing bit errors
E1 – BPV, CV, CRC-4, E-bit, and frame alignment errors
Timed or manual update modes
Three independent generators and detectors
Patterns from 1 bit to 8 bits or 16 bits in length
Software- or hardware-based
Interrupt generated on change of signaling data
Receive-signaling freeze on loss of sync, carrier loss, or frame slip
12 of 269
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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