DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 55
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 55 of 269
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit Yellow Alarm (TYEL).
Bit 1/Transmit Blue Alarm (TBL).
Bit 2/TFDL Register Select (TFDLS).
Bit 3/Global Bit 7 Stuffing (GB7S).
Bit 4/Transmit Software Signaling Enable (TSSE).
Bit 5/Transmit CRC Pass Through (TCPT).
Bit 6/Transmit F-Bit Pass Through (TFPT).
Bit 7/Transmit Japanese CRC6 Enable (TJC).
0 = do not transmit yellow alarm
1 = transmit yellow alarm
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOS and TNEG
0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC controller or the TLINK pin
0 = allow the SSIEx registers to determine which channels containing all zeros are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of how the SSIEx registers are programmed
0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx registers still
define which channels are to have B7 stuffing preformed
1 = source signaling data as enabled by the SSIEx registers
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F-bit time
0 = F bits sourced internally
1 = F bits sampled at TSER
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
TJC
7
0
TFPT
T1TCR1
T1 Transmit Control Register 1
05h
6
0
TCPT
5
0
TSSE
4
0
55 of 269
GB7S
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TFDLS
2
0
TBL
1
0
TYEL
0
0
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