DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 191
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 191 of 269
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/BERT in Synchronization Condition (BSYNC).
Bit 1/Receive Loss Of Synchronization Condition (BRLOS).
Bit 2/Receive All Zeros Condition (BRA0).
Bit 3/Receive All Ones Condition (BRA1).
Bit 4/BERT Error Counter Overflow Event (BECO).
Bit 5/BERT Bit Counter Overflow Event (BBCO).
Bit 6/Bit Error Detected Event (BBED).
BERT Alternating Word Count Rate. When the BERT is programmed in the alternating word mode, the words will repeat
for the count loaded into this register then flip to the other word and again repeat for the number of times loaded into this
register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Alternating Word Count Rate Bits 0 to 7 (ACNT0 to ACNT7). ACNT0 is the LSB of the 8-bit alternating word
count rate counter.
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
ACNT7
7
0
—
7
0
ACNT6
BBED
6
0
IMR9
Interrupt Mask Register 9
27h
BAWC
BERT Alternating Word Count Rate
DBh
6
0
ACNT5
BBCO
5
0
5
0
ACNT4
BEC0
4
0
4
0
191 of 269
ACNT3
BRA1
3
0
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ACNT2
BRA0
2
0
2
0
BRLOS
ACNT1
1
0
1
0
BSYNC
ACNT0
0
0
0
0
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