DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 11
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 11 of 269
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2. FEATURE HIGHLIGHTS
2.1 General
2.2 Line Interface
2.3 Clock Synthesizer
DS21455: 27mm, 1.27 pitch BGA, compatible replacement for the DS21Q55
DS21458: 17mm, 1.00 pitch CSBGA
3.3V supply with 5V tolerant inputs and outputs
Evaluation kits
IEEE 1149.1 JTAG-boundary scan
Driver source code available from the factory
Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be
Fully software configurable
Short- and long-haul applications
Automatic receive sensitivity adjustments
Ranges include 0dB to -43dB or 0dB to -12dB for E1 applications; 0dB to -36dB or 0dB to -15dB
Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
Internal receive termination option for 75Ω, 100Ω, and 120Ω lines
Monitor application gain settings of 20dB, 26dB, and 32dB
G.703 receive-synchronization signal-mode
Flexible transmit-waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
AIS generation independent of loopbacks
Alternating ones and zeros generation
Square-wave output
Open-drain output option
NRZ format option
Transmitter power-down
Transmitter 50mA short-circuit limiter with exceeded indication of current limit
Transmit open-circuit-detected indication
Line interface function can be completely decoupled from the framer/formatter
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Derived from recovered line clock or master clock
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,
6.276MHz, or 12.552MHz for T1-only operation
for T1 applications
11 of 269
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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