DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 172
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 172 of 269
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Loss of Transmit Clock Condition (LOLITC).
Bit 1/Transmit Open Circuit Detect Condition (TOCD).
Bit 2/Transmit Current Limit Exceeded Condition (TCLE).
Bit 3/Line Interface Receive Carrier Loss Condition (LRCL).
Bit 4/Jitter Attenuator Limit Trip Event (JALT).
Bit 5/Receive Signaling Change-of-State Event (RSCOS).
Bit 6/Timer Event (TIMER).
Bit 7/Input Level Under Threshold (ILUT)
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
ILUT
7
0
TIMER
IMR1
Interrupt Mask Register 1
17h
6
0
RSCOS
5
0
JALT
4
0
172 of 269
LRCL
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TCLE
2
0
TOCD
1
0
LOLITC
0
0
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