DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 207
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 207 of 269
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to output their interrupt status
on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Device Receive Loss of Sync (DRLOSn). Causes all devices participating in the ESIB group to output their frame
synchronization status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/User-Selected Status 1 (UST1n). Causes all devices participating in the ESIB group to output status or alarms as
selected by the ESI3SEL0 to ESI3SEL2 bits in the ESIBCR2 configuration register on the appropriate data bus line selected by
the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/User-Selected Status 2 (UST2n). Causes all devices participating in the ESIB group to output status or alarms as
selected by the ESI4SEL0 to ESI4SEL2 bits in the ESIBCR2 configuration register on the appropriate data bus line selected by
the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register.
DRLOSn
UST1n
UST2n
DISn
7
0
7
0
7
0
7
0
DRLOSn
UST1n
UST2n
ESIB1
Extended System Information Bus Register 1
B2h
ESIB2
Extended System Information Bus Register 2
B3h
ESIB3
Extended System Information Bus Register 3
B4h
ESIB4
Extended System Information Bus Register 4
B5h
DISn
6
0
6
0
6
0
6
0
DRLOSn
UST1n
UST2n
DISn
5
0
5
0
5
0
5
0
DRLOSn
UST1n
UST2n
DISn
4
0
4
0
4
0
4
0
207 of 269
DRLOSn
UST1n
UST2n
DISn
3
0
3
0
3
0
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
DRLOSn
UST1n
UST2n
DISn
2
0
2
0
2
0
2
0
DRLOSn
UST1n
UST2n
DISn
1
0
1
0
1
0
1
0
DRLOSn
UST1n
UST2n
DISn
0
0
0
0
0
0
0
0
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