S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 86

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

86
10.3.13
10.3.14
AutoBoot Register Write (ABWR 15h)
Program NVDLR (PNVDLR 43h)
Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write
operations.
The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first,
most significant bit of each byte first. The ABWR data is 32 bits in length.
The ABWR command has status reported in Status Register-1 as both an erase and a programming
operation. An E_ERR or a P_ERR may be set depending on whether the erase or programming phase of
updating the register fails.
CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR
command is not executed. As soon as CS# is driven to the logic high state, the self-timed ABWR operation is
initiated. While the ABWR operation is in progress, Status Register-1 may be read to check the value of the
Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ABWR operation, and
is a 0. when it is completed. When the ABWR cycle is completed, the Write Enable Latch (WEL) is set to a 0.
The maximum clock frequency for the ABWR command is 133 MHz.
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the
PNVDLR command is not executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR
operation is initiated. While the PNVDLR operation is in progress, the Status Register may be read to check
the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed
PNVDLR cycle, and is a 0. when it is completed. The PNVDLR operation can report a program error in the
P_ERR bit of the status register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is
set to a 0 The maximum clock frequency for the PNVDLR command is 133 MHz.
Phase
SCK
CS#
SO
SI
Phase
SCK
CS#
SO
SI
7
7 6 5 4 3 2 1 0
Figure 10.18 AutoBoot Register Read (ABRD 14h) Command
6
Figure 10.19 AutoBoot Register Write (ABWR) Command
Instruction
5
D a t a
Instruction
4
S25FL512S
3
S h e e t
2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1
( P r e l i m i n a r y )
0
Data 1
7
6
5
Input Data 1
4
S25FL512S_00_04 June 13, 2012
Data N
3
2
1
0
7