S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 84

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

84
10.3.10
10.3.11
Clear Status Register (CLSR 30h):
AutoBoot
The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It
is not necessary to set the WEL bit before the Clear SR command is executed. The Clear SR command will
be accepted even when the device remains busy with WIP set to 1, as the device does remain busy when
either error bit is set. The WEL bit will be unchanged after this command is executed.
SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command.
And, in order to read boot code from an SPI device, the host memory controller or processor must supply the
read command from a hardwired state machine or from some host processor internal ROM code.
Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time
to start reading boot code.
The AutoBoot feature allows the host memory controller to take boot code from an S25FL512S device
immediately after the end of reset, without having to send a read command. This saves 32 or more cycles and
simplifies the logic needed to initiate the reading of boot code.
 As part of the power up reset, hardware reset, or command reset process the AutoBoot feature
 The starting address of the boot code is selected by the value programmed into the AutoBoot Start
 At any point after the first data byte is transferred, when CS# returns high, the SPI device will reset to
automatically starts a read access from a pre-specified address. At the time the reset process is
completed, the device is ready to deliver code from the starting address. The host memory controller only
needs to drive CS# signal from high to low and begin toggling the SCK signal. The S25FL512S device will
delay code output for a pre-specified number of clock cycles before code streams out.
Address (ABSA) field of the AutoBoot Register which specifies a 512 byte boundary aligned location; the
default address is 00000000h.
standard SPI mode; able to accept normal command operations.
Phase
– The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is
– The host cannot send commands during this time.
– If ABSD = 0, the maximum SCK frequency is 50 MHz.
– If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is 0 or 104 MHz if the
– Data will continuously shift out until CS# returns high.
– A minimum of one byte must be transferred.
– AutoBoot mode will not initiate again until another power cycle or a reset occurs.
SCK
Phase
CS#
SO
SCK
CS#
needed by the host.
QUAD bit is set to 1.
SI
SO
SI
Figure 10.15 Clear Status Register (CLSR 30h) Command Sequence
Figure 10.14 Write Disable (WRDI 04h) Command Sequence
7
7
D a t a
6
6
S25FL512S
S h e e t
5
5
4
Instruction
( P r e l i m i n a r y )
4
Instruction
3
3
2
2
S25FL512S_00_04 June 13, 2012
1
1
0
0