S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 139
![no-image](/images/no-image-200.jpg)
S25FL512SAGMFIG13
Manufacturer Part Number
S25FL512SAGMFIG13
Description
Flash 512Mb 3V 133MHz Serial NOR Flash
Manufacturer
Spansion
Datasheet
1.S25FL512SAGMFI011.pdf
(143 pages)
Specifications of S25FL512SAGMFIG13
Rohs
yes
Memory Type
Flash
Memory Size
512 MB
Architecture
Uniform
Timing Type
Asynchronous
Interface Type
SPI
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
SO-16
- Current page: 139 of 143
- Download datasheet (5Mb)
11.5
June 13, 2012 S25FL512S_00_04
Initial Delivery State
The device is shipped from Spansion with non-volatile bits set as follows:
The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).
The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased
The SFDP address space contains the values as defined in the description of the SFDP address space.
The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.
The Status Register 1 contains 00h (all SR1 bits are cleared to 0’s).
The Configuration Register 1 contains 00h.
The Autoboot register contains 00h.
The Password Register contains FFFFFFFF-FFFFFFFFh
All PPB bits are 1.
The ASP Register contents depend on the ordering options selected:
7 to 0
7 to 0
Bits
Bits
to FFh.
Field Name
Field Name
NVDLP
VDLP
D a t a
01, 21, 31, R1, A1, B1, C1, D1,
Ordering Part Number Model
M1, N1, U1, V1, W1, X1
K1, L1. S1, T1, Y1, Z1,
91, Q1, 71, 61, 81
Data Learning
Volatile Data
Non-Volatile
S h e e t
Function
Function
Learning
Pattern
Pattern
Table 11.29 Non-Volatile Data Learning Register (NVDLR)
Table 11.30 Volatile Data Learning Register (NVDLR)
( P r e l i m i n a r y )
Volatile
Type
Type
OTP
Table 11.31 ASP Register Content
S25FL512S
Default State
Default State
during POR
Takes the
or Reset
value of
NVDLR
00h
OTP value that may be transferred to the host during DDR read
command latency (dummy) cycles to provide a training pattern to
help the host more accurately center the data capture point in the
received data bits.
Volatile copy of the NVDLP used to enable and deliver the Data
Learning Pattern (DLP) to the outputs. The VDLP may be changed
by the host during system operation.
ASPR Default Value
Description
Description
FE7Fh
FE4Fh
139
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