S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 22

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

4.2
22
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
Command Protocol
All communication between the host system and S25FL512S memory device is in the form of units called
commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be
performed. Commands may also have an address, instruction modifier, latency period, data transfer to the
memory, or data transfer from the memory. All instruction, address, and data information is transferred
serially between the host system and memory device.
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back
to the host serially on the SO signal.
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be
returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,
and IO3.
Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1
or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0
and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Commands are structured as follows:
 Each command begins with CS# going low and ends with CS# returning high. The memory device is
 The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
 Each command begins with an eight bit (byte) instruction. The instruction is always presented only as a
 The instruction may be stand alone or may be followed by address bits to select a location within one of
 The width of all transfers following the instruction are determined by the instruction sent. Following
 Some instructions send an instruction modifier called mode bits, following the address, to indicate that the
Transfer_Phase
selected by the host driving the Chip Select (CS#) signal low throughout a command.
single bit serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on
each SCK rising edge. The instruction selects the type of information transfer or device operation to be
performed.
several address spaces in the device. The instruction determines the address space used. The address
may be either a 24-bit or a 32-bit byte boundary, address. The address transfers occur on SCK rising edge,
in SDR commands, or on every SCK edge, in DDR commands.
transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done
in two bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4 bit groups per
(quad) transfer on the IO0-IO3 signals. Within the dual or quad groups the least significant bit is on IO0.
More significant bits are placed in significance order on each higher numbered IO signal. SIngle bits or
parallel bit groups are transferred in most to least significant bit order.
next command will be of the same type with an implied, rather than an explicit, instruction. The next
CS#
SO
SI
Instruction
Inst. 7
Figure 4.2 SPI DDR Modes Supported
D a t a
Inst. 0
S25FL512S
S h e e t
Address
A 3 1
A 3 0
A0
( P r e l i m i n a r y )
M 7 M 6
Mode
M 0
Dummy / DLP
D L P 7
S25FL512S_00_04 June 13, 2012
D L P 0
D0 D1
Read
Data