S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 80

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

80
10.3.5
10.3.6
Bank Register Write (BRWR 17h)
Bank Register Access (BRAC B9h):
The Bank Register Write (BRWR) command is used to write address bits above A23, into the Bank Address
Register (BAR). The command is also used to write the Extended address control bit (EXTADD) that is also in
BAR[7]. BAR provides the high order addresses needed by devices having more than 128 Mbits (16 Mbytes),
when using 3-byte address commands without extended addressing enabled (BAR[7] EXTADD = 0).
Because this command is part of the addressing method and is not changing data in the flash memory, this
command does not require the WREN command to precede it.
The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in
length.
The BRWR command has no effect on the P_ERR, E_ERR or WIP bits of the Status and Configuration
Registers. Any bank address bit reserved for the future should always be written as a 0.
The Bank Register Read and Write commands provide full access to the Bank Address Register (BAR) but
they are both commands that are not present in legacy SPI memory devices. Host system SPI memory
controller interfaces may not be able to easily support such new commands. The Bank Register Access
(BRAC) command uses the same command code and format as the Deep Power Down (DPD) command that
is available in legacy SPI memories. The FL-S family does not support a DPD feature but assigns this legacy
command code to the BRAC command to enable write access to the Bank Address Register for legacy
systems that are able to send the legacy DPD (B9h) command.
When the BRAC command is sent, the FL-S family device will then interpret an immediately following Write
Register (WRR) command as a write to the lower address bits of the BAR. A WREN command is not used
between the BRAC and WRR commands. Only the lower two bits of the first data byte following the WRR
command code are used to load BAR[1:0]. The upper bits of that byte and the content of the optional WRR
command second data byte are ignored. Following the WRR command the access to BAR is closed and the
device interface returns to the standby state. The combined BRAC followed by WRR command sequence has
no affect on the value of the ExtAdd bit (BAR[7]).
Commands other than WRR may immediately follow BRAC and execute normally. However, any command
other than WRR, or any other sequence in which CS# goes low and returns high, following a BRAC
command, will close the access to BAR and return to the normal interpretation of a WRR command as a write
to Status Register-1 and the Configuration Register.
The BRAC + WRR sequence is allowed only when the device is in standby, program suspend, or erase
suspend states. This command sequence is illegal when the device is performing an embedded algorithm or
when the program (P_ERR) or erase (E_ERR) status bits are set to 1.
Phase
SCK
CS#
Phase
SO
SI
SCK
CS#
SO
SI
7
7
6
6
5
Instruction
Figure 10.9 Bank Register Write (BRWR 17h) Command
Figure 10.8 Read Bank Register (BRRD 16h) Command
4
5
Instruction
3
D a t a
4
2
3
1
S25FL512S
S h e e t
0
2
7
1
6
Register Read
5
0
( P r e l i m i n a r y )
4
7
3
2
6
1
5
0
Input Data
4
7
Repeat Register Read
S25FL512S_00_04 June 13, 2012
6
3
5
2
4
3
1
2
0
1
0