S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 114

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

114
10.8.3
10.8.4
10.8.5
DYB Read (DYBRD E0h)
DYB Write (DYBWR E1h)
PPB Read (PPBRD E2h)
The instruction E0h is latched into SI by the rising edge of the SCK signal. Followed by the 32-bit address
selecting location zero within the desired sector (note, the high order address bits not used by a particular
density device must be zero). Then the 8-bit DYB access register contents are shifted out on the serial output
SO. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read
the same DYB access register continuously by providing multiples of eight clock cycles. The address of the
DYB register does not increment so this is not a means to read the entire DYB array. Each location must be
read with a separate DYB Read command. The maximum operating clock frequency for READ command is
133 MHz.
Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command
must be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
The DYBWR command is entered by driving CS# to the logic low state, followed by the instruction, the 32-bit
address selecting location zero within the desired sector (note, the high order address bits not used by a
particular density device must be zero), then the data byte on SI. The DYB Access Register is one data byte
in length.
The DYBWR command affects the P_ERR and WIP bits of the Status and Configuration Registers in the
same manner as any other programming operation. CS# must be driven to the logic high state after the eighth
bit of data has been latched in. If not, the DYBWR command is not executed. As soon as CS# is driven to the
logic high state, the self-timed DYBWR operation is initiated. While the DYBWR operation is in progress, the
Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress
(WIP) bit is a 1 during the self-timed DYBWR operation, and is a 0 when it is completed. When the DYBWR
operation is completed, the Write Enable Latch (WEL) is set to a 0.
The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 32-bit address
selecting location zero within the desired sector (note, the high order address bits not used by a particular
density device must be zero) Then the 8-bit PPB access register contents are shifted out on SO.
It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles.
The address of the PPB register does not increment so this is not a means to read the entire PPB array. Each
Phase
Phase
SCK
CS#
SCK
CS#
S O
SO
SI
S I
7
7
6
Instruction
5
6
4 3
5
Instruction
4
2
Figure 10.64 DYBWR (E1h) Command Sequence
3
D a t a
1 0 31
Figure 10.63 DYBRD Command Sequence
2
1
Address
S25FL512S
0 31
S h e e t
1 0
7
5
Address
( P r e l i m i n a r y )
6 5
4
Register
3
4
2
3 2
1
0
1
7
0
S25FL512S_00_04 June 13, 2012
7 6
6
Repeat Register
5
Input Data
5
4
4
3
3
2
2 1 0
1
0