S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 28

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

28
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Low Power Hardware Data Protection
Power-On (Cold) Reset
Hardware (Warm) Reset
Interface Standby
Instruction Cycle
Hold
When V
erase operations can not start when the core supply voltage is out of the operating range.
When the core voltage supply remains at or below the V
(Minimum)
t
device transitions to the Interface Standby state and can accept commands. For additional information on
POR see
Some of the device package options provide a RESET# input. When RESET# is driven low for t
device starts the hardware reset process. The process continues for t
and the reset hold time following the rise of RESET# (t
and can accept commands. For additional information on hardware reset see
Reset on page
When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface
waits for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes low
to begin a new command.
While in interface standby state the memory device draws standby current (I
in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the
algorithm when the entire device returns to standby current draw.
When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device
captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the
device captures the next lower significance bit of the 8 bit instruction. The host keeps RESET# high, CS# low,
HOLD# high, and drives Write Protect (WP#) signal as needed for the instruction. However, WP# is only
relevant during instruction cycles of a WRR command and is otherwise ignored.
Each instruction selects the address space that is operated on and the transfer format used during the
remainder of the command. The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O,
DDR Single I/O, DDR Dual I/O, or DDR Quad I/O. The expected next interface state depends on the
instruction received.
Some commands are stand alone, needing no address or data transfer to or from the memory. The host
returns CS# high after the rising edge of SCK for the eighth bit of the instruction in such commands. The next
interface state in this case is Interface Standby.
When Quad mode is not enabled (CR[1]=0) the HOLD# / IO3 signal is used as the HOLD# input. The host
keeps RESET# high, HOLD# low, SCK may be at a valid level or continue toggling, and CS# is low. When
HOLD# is low a command is paused, as though SCK were held low. SI / IO0 and SO / IO1 ignore the input
level when acting as inputs and are high impedance when acting as outputs during hold state. Whether these
signals are input or output depends on the command and the point in the command sequence when HOLD#
is asserted low.
When HOLD# returns high the next state is the same state the interface was in just before HOLD# was
asserted low.
When Quad mode is enabled the HOLD# / IO3 signal is used as IO3.
During DDR commands the HOLD# and WP# inputs are ignored.
PU
the device does not react to external input signals nor drive any outputs. Following the end of t
CC
the device will begin its Power On Reset (POR) process. POR continues until the end of t
Power-On (Cold) Reset on page
is less than V
39.
CC
(cut-off) the memory device will ignore commands to ensure that program and
D a t a
S25FL512S
S h e e t
38.
RH
( P r e l i m i n a r y )
CC
) the device transitions to the Interface Standby state
(low) voltage for  t
RPH
time. Following the end of both t
SB
S25FL512S_00_04 June 13, 2012
POR followed by Hardware
) if no embedded algorithm is
PD
time, then rises to  V
RP
PU
PU
time the
. During
the
CC
RPH