S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 116

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

116
10.8.8
10.8.9
10.8.10
PPB Lock Bit Read (PLBRD A7h):
PPB Lock Bit Write (PLBWR A6h):
Password Read (PASSRD E7h)
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is
possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock
Register contents may only be read when the device is in standby state with no other operation in progress. It
is recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new
command to the device.
The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR
command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by
the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the
PLBWR command is not executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR
operation is initiated. While the PLBWR operation is in progress, the Status Register may still be read to
check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed
PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed, the Write
Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.
The correct password value may be read only after it is programmed and before the Password Mode has
been selected by programming the Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the
Password Protection Mode is selected the PASSRD command is ignored.
The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO,
least significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK frequency by
Phase
Phase
Phase
SCK
CS#
SCK
CS#
SO
SCK
SO
CS#
SI
SI
SO
SI
7
Figure 10.68 PPB Lock Register Read Command Sequence
6
Figure 10.69 PPB Lock Bit Write (PLBWR A6h) Command Sequence
5
Instruction
Figure 10.67 PPB Erase (PPBE E4h) Command Sequence
7
4
7
3
D a t a
2
6
6
1
0
S25FL512S
S h e e t
7
5
5
6
Register Read
5
4
Instruction
4
Instruction
( P r e l i m i n a r y )
4
3
2
3
3
1
0
2
7
2
Repeat Register Read
6
S25FL512S_00_04 June 13, 2012
5
1
1
4
3
0
2
0
1
0