S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 102

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

102
10.4.9
Figure 10.45 Continuous DDR Dual I/O Read Subsequent Access (4-byte Address, EHPLC= 01b)
DDR Quad I/O Read (EDh, EEh)
characterized the optimal data capture point can be chosen. See
Registers on page 63
The Read DDR Quad I/O command improves throughput with four I/O signals - IO0-IO3. It is similar to the
Quad I/O Read command but allows input of the address four bits on every edge of the clock. In some
applications, the reduced instruction overhead might allow for code execution (XIP) directly from the
S25FL512S device. The QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad
capability.
The instruction
 EDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 EDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 EEh is followed by a 4-byte address (A31-A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a
DDR fashion, with four bits at a time on each clock edge through IO0-IO3.
The maximum operating clock frequency for Read DDR Quad I/O command is 66 MHz.
For Read DDR Quad I/O, there is a latency required after the last address and mode bits are shifted into the
IO0-IO3 signals before data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the
device’s internal circuitry enough time to access the initial address. During these latency cycles, the data
Figure 10.46 DDR Dual I/O Read (4-byte Address, BEh or BDh [ExtAdd=1], HPLC=00b)
Phase
Phase
Phase
SCK
CS#
SCK
IO0
IO1
CS#
SCK
CS#
IO0
IO1
IO0
IO1
7
30
31
7
(4-byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b)
6
Address
6
Figure 10.44 DDR Dual I/O Read Initial Access
for more details.
5
2
3
Instruction
5
4
0
1
Instruction
4
6
7
3
D a t a
Mode
4
5
3
2
2
3
S25FL512S
2
1
S h e e t
0
1
1
0
Dummy
3 0 2 8
3 1 2 9
Address
0
30
31
Address
7
7
( P r e l i m i n a r y )
0
1
6
6
6
7
2 0
3 1
Mode
4
5
4
4
2
3
5
5
Section 8.6.11, SPI DDR Data Learning
1
0
DLP
Dum
3
3
7 6
7 6
Dummy
2 1
2 1
S25FL512S_00_04 June 13, 2012
5 4
5 4
DLP
0
0
3
3
2
2
6
7
1 0
1 0
Data 1
4
5
6
7
2
3
Data 1
6 4 2 0 6
7 5 3 1 7
Data 1
4
5
2
3
0
1
0
1
6
7
6
7
D 2
D 2