C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 414

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
30.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
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Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Figure 30.2. Multiple-Master Mode Connection Diagram
Device 1
Master
Master
Device
Master
Device
GPIO
MISO
MOSI
MISO
MOSI
MISO
MOSI
GPIO
NSS
SCK
SCK
SCK
NSS
Rev. 0.5
GPIO
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
NSS
Device 2
Master
Device
Device
Device
Slave
Slave
Slave