C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 381

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

28. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 28.1.
S
V
L
6
M
A
S
T
E
R
Interrupt
Request
S
L
V
5
M
X
O
D
E
T
SMB0ADR
S
L
V
4
SMB0CN
S
T
A
S
V
L
3
O
S
T
S
V
L
2
A
C
K
R
Q
S
L
V
1
A
R
B
O
S
L
T
S
V
L
0
C
A
K
G
C
S
I
M
S
V
L
6
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
Hardware ACK Generation
IRQ Generation
S
V
M
SMBUS CONTROL LOGIC
L
5
SMB0ADM
M
S
L
V
4
M
S
V
L
3
M
S
V
L
2
M
E
N
S
B
Figure 28.1. SMBus Block Diagram
M
S
L
V
1
N
H
I
M
S
V
L
0
SMB0CF
B
U
S
Y
E
H
A
C
K
E
X
T
H
O
D
L
S
M
B
O
E
T
M
S
B
F
T
E
M
S
B
C
S
1
7
M
S
B
C
S
0
6
Data Path
SMB0DAT
5
Control
4
3
Rev. 0.5
2
1
0
00
01
10
11
Control
SDA
Control
SCL
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
2
N
N
C serial bus. Reads and writes to
SDA
SCL
O
C
R
S
S
B
A
R
C8051F96x
Port I/O
381