C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 147

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

11.1. DMA0 Architecture
The first step in configuring a DMA0 channel is to select the desired channel for data transfer using
DMA0SEL[2:0] bits (DMA0SEL). After setting the DMA0 channel, firmware can address channel-specific
registers such as DMA0NCF, DMA0NBAH/L, DMA0NAOH/L, and DMA0NSZH/L. Once firmware selects a
channel, the subsequent SFR configuration applies to the DMA0 transfer of that selected channel.
Each DMA0 channel consists of an SFR assigning the channel to a peripheral, a channel control register
and a set of SFRs that describe XRAM and SFR addresses to be used during data transfer (See
Figure 11.1). The peripheral assignment bits of DMA0nCF select one of the eight data transfer functions.
The selected channel can choose the desired function by writing to the PERIPH[2:0] bits (DMA0NCF[2:0]).
The control register DMA0NCF of each channel configures the endian-ness of the data in XRAM, stall
enable, full-length interrupt enable and mid-point interrupt enable. When a channel is stalled by setting the
STALL bit (DMA0NCF.5), DMA0 transfers in progress will not be aborted, but new DMA0 transfers will be
blocked until the stall status of the channel is reset. After the stall bit is set, software should poll the corre-
sponding DMA0BUSY to verify that there are no more DMA transfers for that channel.
The memory interface configuration SFRs of a channel define the linear region of XRAM involved in the
transfer through a 12-bit base address register DMA0NBAH:L, a 10-bit address offset register
DMA0NAOH:L and a 10-bit data transfer size DMA0NSZH:L. The effective memory address is the address
involved in the current DMA0 transaction.
The address offset serves as byte counter. The address offset should be always less than data transfer
length. The address offset increments by one after each byte transferred. For DMA0 configuration of any
channel, address offsets of active channels should be reset to 0 before DMA0 transfers occur.
Common
Control/
SPI1 to XRAM request
XRAM to AES0KIN request
XRAM to AES0BIN request
XRAM to AES0XIN request
AES0YOUT to XRAM request
XRAM to ENC0 request
ENC0 to XRAM request
XRAM to CRC1 request
XRAM to SPI1 request
Status
DMA0SEL
Peripheral assignment -
Effective Memory Address = Base Address + Address Offset
DMA0nCF[2:0]
DMA0BUSY
Figure 11.1. DMA0 Block Diagram
DMA0nMD
Channel
DMA0nCF
Control
DMA0MINT
Channel 6
Channel 1
Channel 0
Rev. 0.5
DMA0nBAH
DMA0nAOH
DMA0nSZH
DMA0INT
Channel memory
interface config
DMA0nAOL
DMA0nBAL
DMA0nSZL
DMA0EN
Internal
control
DMA
bus
C8051F96x
ENGINE
DMA
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