C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 240

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2
SFR Page = All Pages;SFR Address = 0xE7
240
Name
Reset
Type
Bit
Bit
7
6
5
4
3
2
1
0
ERTC0F
EDMA0 Enable DMA0 Interrupt.
EAES0 Enable AES0 Interrupt.
EWARN
EENC0
Name
ESPI1
EMAT
EPC0
EAES0
R/W
7
0
This bit sets the masking of AES0 interrupts.
0: Disable all AES0 interrupts.
1: Enable interrupt requests generated by AES0.
Enable Encoder (ENC0) Interrupt.
This bit sets the masking of ENC0 interrupts.
0: Disable all ENC0 interrupts.
1: Enable interrupt requests generated by ENC0.
This bit sets the masking of DMA0 interrupts.
0: Disable all DMA0 interrupts.
1: Enable interrupt requests generated by DMA0.
Enable Pulse Counter (PC0) Interrupt.
This bit sets the masking of PC0 interrupts.
0: Disable all PC0 interrupts.
1: Enable interrupt requests generated by PC0.
Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
Enable VDD/DC+ Supply Monitor Early Warning Interrupt.
This bit sets the masking of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: Disable the VDD/DC+ Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD/DC+ Supply Monitor.
EENC0
R/W
6
0
EDMA0
R/W
5
0
EPC0
R/W
Rev. 0.5
4
0
Function
ESPI1
R/W
3
0
ERTC0F
R/W
2
0
EMAT
R/W
1
0
EWARN
R/W
0
0