C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 343
C8051F962-A-GM
Manufacturer Part Number
C8051F962-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F962-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
DQFN-76
Mounting Style
SMD/SMT
Number Of Programmable I/os
57
Number Of Timers
4
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SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration
SFR Page = 0x2; SFR Address = 0xAC
SFR Definition 26.6. LCD0PWR: LCD0 Power
SFR Page = 0x2; SFR Address = 0xA4
Name
Reset
Name
Reset
Bit
7:2
Bit
7:4
2:0
Type
Type
1
0
3
Bit
Bit
DCENSLP
Reserved
Reserved
CHPBYP
Unused
MODE
Name
Name
R/W
R/W
7
1
7
0
Read = 111111b. Must write 111111b.
DCDC Converter Enable in Sleep Mode
0: DCDC is disabled in Sleep Mode.
1: DCDC is enabled in Sleep Mode.
LCD0 Charge Pump Bypass
This bit should be set to 1b in Contrast Control Mode 1 and Mode 2.
0: LCD0 Charge Pump is not bypassed.
1: LCD0 Charge Pump is bypassed.
Read = 0000b. Write = don’t care.
LCD0 Contrast Control Mode Selection.
0: LCD0 Contrast Control Mode 1 or Mode 4 is selected.
1: LCD0 Contrast Control Mode 2 or Mode 3 is selected.
Read = 001b. Must write 001b.
R/W
R/W
6
1
6
0
R/W
R/W
5
1
5
0
Rev. 0.5
R/W
R/W
4
1
4
0
Function
Function
MODE
R/W
R/W
3
1
3
1
R/W
R/W
2
1
2
0
C8051F96x
DCENSLP CHPBYP
R/W
R/W
1
1
1
0
R/W
R/W
0
0
0
1
343
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