C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 334

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
26. LCD Segment Driver
C8051F96x devices contain an LCD segment driver and on-chip bias generation that supports static, 2-
mux, 3-mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output
voltage allows software contrast control which is independent of the supply voltage. LCD timing is derived
from the SmaRTClock oscillator to allow precise control over the refresh rate.
The C8051F96x uses special function registers (SFRs) to store the enabled/disabled state of individual
LCD segments. All LCD waveforms are generated on-chip based on the contents of the LCD0Dn registers
An LCD blinking function is also supported. A block diagram of the LCD segment driver is shown in
Figure 26.1.
26.1. Configuring the LCD Segment Driver
The LCD segment driver supports multiple mux options: static, 2-mux, 3-mux, and 4-mux mode. It also
supports 1/2 and 1/3 bias options. The desired mux mode and bias is configured through the LCD0CN reg-
ister. A divide value may also be applied to the SmaRTClock output before being used as the LCD0 clock
source.
The following procedure is recommended for using the LCD Segment Driver:
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1. Initialize the SmaRTClock and configure the LCD clock divide settings in the LCD0CN register.
2. Determine the GPIO pins which will be used for the LCD function.
3. Configure the Port I/O pins to be used for LCD as Analog I/O.
4. Configure the LCD size, mux mode, and bias using the LCD0CN register.
5. Enable the LCD bias and clock gate by writing 0x50 to the LCD0MSCN register.
6. Configure the device into the desired Contrast Control Mode.
7. If VIO is internally or externally shorted to VBAT, disable the VLCD/VIO Supply Comparator using the
SmaRTClock
VBAT
Charge
Pump
Divider
Clock
LCD Clock
Figure 26.1. LCD Segment Driver Block Diagram
Management
Power
Configuration
Registers
LCD State Machine
VLCD
Rev. 0.5
Data Registers
10 uF
Generator
LCD Segment Driver
Bias
Drivers
Port
32 Segment
4 COM Pins
Pins