ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 68

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Reading the Pin Value
68
ATmega128
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to one to
disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 25
Table 25. Port Pin Configurations
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also introduces a delay.
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted t
Figure 31. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
DDxn
0
0
0
1
1
INSTRUCTIONS
summarizes the control signals for the pin value.
PORTxn
SYSTEM CLK
SYNC LATCH
0
1
1
0
1
PINxn
(in SFIOR)
r17
PUD
X
X
X
0
1
Figure
Output
Output
pd,max
Input
Input
Input
I/O
XXX
and t
30, the PINxn Register bit and the preceding latch consti-
Pull-up
Yes
pd,min
No
No
No
No
respectively.
t
pd, max
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
0x00
XXX
t
pd, min
Figure 31
in r17, PINx
shows a timing diagram of
0xFF
2467S–AVR–07/09