ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 132

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

132
ATmega128
Figure 57
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn flag at BOTTOM.
Figure 57. Timer/Counter Timing Diagram, no Prescaling
Figure 58
Figure 58. Timer/Counter Timing Diagram, with Prescaler (f
(PC and PFC PWM)
(PC and PFC PWM)
and ICFn
and ICFn
(CTC and FPWM)
(CTC and FPWM)
TOVn
(Update at TOP)
TOVn
(Update at TOP)
TCNTn
TCNTn
OCRnx
TCNTn
TCNTn
OCRnx
as TOP)
as TOP)
(clk
(clk
shows the same timing data, but with the prescaler enabled.
clk
clk
shows the count sequence close to TOP in various modes. When using phase and
clk
clk
I/O
I/O
(FPWM)
(FPWM)
I/O
Tn
I/O
Tn
/1)
/8)
(if used
(if used
TOP - 1
TOP - 1
TOP - 1
TOP - 1
Old OCRnx Value
Old OCRnx Value
TOP
TOP
TOP
TOP
clk_I/O
BOTTOM
BOTTOM
/8)
TOP - 1
TOP - 1
New OCRnx Value
New OCRnx Value
BOTTOM + 1
BOTTOM + 1
2467S–AVR–07/09
TOP - 2
TOP - 2