ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 180

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Parity Generator
Disabling the Transmitter
Data Reception – The
USART Receiver
Receiving Frames with 5 to 8
Data Bits
180
ATmega128
transmission is used, the data register empty Interrupt routine must either write new
data to UDR in order to clear UDRE or disable the data register empty interrupt, other-
wise a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit
Shift Register has been shifted out and there are no new data currently present in the
transmit buffer. The TXC flag bit is automatically cleared when a transmit complete inter-
rupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag is
useful in half-duplex communication interfaces (like the RS485 standard), where a
transmitting application must enter receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART
Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided
that global interrupts are enabled). When the transmit complete interrupt is used, the
interrupt handling routine does not have to clear the TXC flag, this is done automatically
when the interrupt is executed.
The parity generator calculates the parity bit for the serial frame data. When parity bit is
enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last
data bit and the first stop bit of the frame that is sent.
The disabling of the Transmitter (setting the TXEN to zero) will not become effective
until ongoing and pending transmissions are completed, i.e., when the Transmit Shift
Register and Transmit Buffer register do not contain data to be transmitted. When dis-
abled, the Transmitter will no longer override the TxD pin.
The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the
UCSRB Register to one. When the receiver is enabled, the normal pin operation of the
RxD pin is overridden by the USART and given the function as the receiver’s serial
input. The baud rate, mode of operation and frame format must be set up once before
any serial reception can be done. If synchronous operation is used, the clock on the
XCK pin will be used as transfer clock.
The Receiver starts data reception when it detects a valid start bit. Each bit that follows
the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive
Shift Register until the first stop bit of a frame is received. A second stop bit will be
ignored by the receiver. When the first stop bit is received, i.e., a complete serial frame
is present in the Receive Shift Register, the contents of the Shift Register will be moved
into the receive buffer. The receive buffer can then be read by reading the UDR I/O
location.
2467S–AVR–07/09