ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 204

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Overview of the
TWI Module
Scl and SDA Pins
Bit Rate Generator
Unit
Bus Interface Unit
204
ATmega128
The TWI module is comprised of several submodules, as shown in
in a thick line are accessible through the AVR data bus.
Figure 94. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
•
•
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-
ter is not directly accessible by the application software. However, when receiving, it can be set
TWBR = Value of the TWI Bit Rate Register
TWPS = Value of the prescaler bits in the TWI Status Register
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus
line load. See
Slew-rate
Address Match Unit
Control
Arbitration detection
START / STOP
Address Comparator
Address Register
SCL
Control
(TWAR)
Spike
Filter
Table 133 on page 322
Bus Interface Unit
SCL frequency
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
for value of pull-up resistor.
SDA
=
Status Register
---------------------------------------------------------- -
16
CPU Clock frequency
Ack
Spike
Filter
(TWSR)
+
2(TWBR) 4
State Machine and
Control Unit
Status control
⋅
TWPS
Control Register
Bit Rate Generator
Figure
(TWCR)
Bit Rate Register
Prescaler
(TWBR)
94. All registers drawn
2467S–AVR–07/09