ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 45

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Power
Management
and Sleep
Modes
MCU Control Register
– MCUCR
2467S–AVR–07/09
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register
select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or
Extended Standby) will be activated by the SLEEP instruction. See
an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is
then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the register file and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Figure 18 on page 36
tion. The figure is helpful in selecting an appropriate sleep mode.
The MCU Control Register contains control bits for power management.
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the Sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the Sleep mode unless it is the pro-
grammers purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the
execution of the SLEEP instruction and to clear it immediately after waking up.
• Bits 4..2 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the six available sleep modes as shown in
Table 17. Sleep Mode Select
Note:
Bit
Read/Write
Initial Value
SM2
0
0
0
0
1
1
1
1
1. Standby mode and Extended Standby mode are only available with external crystals or
resonators.
SRE
R/W
7
0
SM1
0
0
1
1
0
0
1
1
SRW10
presents the different clock systems in the ATmega128, and their distribu-
R/W
6
0
R/W
SE
5
0
SM0
0
1
0
1
0
1
0
1
SM1
R/W
4
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
Reserved
Reserved
Standby
Extended Standby
SM0
R/W
3
0
(1)
SM2
R/W
2
0
(1)
IVSEL
R/W
1
0
Table 17
Table
IVCE
R/W
ATmega128
0
0
17.
for a summary. If
MCUCR
45