ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 139

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Output Compare
Register 3 B –
OCR3BH and OCR3BL
Output Compare
Register 3 C –
OCR3CH and OCR3CL
Input Capture Register
1 – ICR1H and ICR1L
Input Capture Register
3 – ICR3H and ICR3L
Timer/Counter
Interrupt Mask
Register – TIMSK
2467S–AVR–07/09
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other
16-bit registers.
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Cap-
ture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit
registers.
Note:
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer sections.
See “Accessing 16-bit Registers” on page 115.
OCIE2
R/W
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
7
0
See “Accessing 16-bit Registers” on page 115.
TOIE2
R/W
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
6
0
TICIE1
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
5
0
OCIE1A
R/W
R/W
R/W
R/W
R/W
OCR3B[15:8]
OCR3C[15:8]
4
0
4
0
4
0
4
0
OCR3B[7:0]
OCR3C[7:0]
4
0
ICR1[15:8]
ICR3[15:8]
ICR1[7:0]
ICR3[7:0]
OCIE1B
R/W
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
3
0
TOIE1
R/W
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
2
0
OCIE0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
1
0
TOIE0
R/W
R/W
R/W
R/W
R/W
ATmega128
0
0
0
0
0
0
0
0
0
0
OCR3BH
OCR3CH
OCR3BL
OCR3CL
ICR1H
ICR3H
ICR1L
ICR3L
TIMSK
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