ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 21

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Data Memory Access
Times
EEPROM Data
Memory
EEPROM Read/Write
Access
EEPROM Address
Register – EEARH and
EEARL
2467S–AVR–07/09
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 10. On-chip Data SRAM Access Cycles
The ATmega128 contains 4K bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
“Memory Programming” on page 286
in SPI, JTAG, or Parallel Programming mode
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used.
ing EEPROM Corruption” on page 25.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
• Bits 15..12 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
Bit
Read/Write
Initial Value
EEAR7
R/W
15
R
0
X
–
7
EEAR6
R/W
14
Address
R
X
–
6
0
clk
Data
Data
WR
CPU
RD
EEAR5
R/W
13
–
5
R
0
X
Compute Address
T1
Memory access instruction
contains a detailed description on EEPROM programming
EEAR4
for details on how to avoid problems in these situations.
R/W
12
R
X
–
4
0
Address valid
EEAR11
EEAR3
R/W
R/W
T2
11
3
X
X
CPU
Table
cycles as described in
EEAR10
EEAR2
Next instruction
R/W
R/W
10
X
X
2
2. A self-timing function, however, lets
T3
EEAR9
EEAR1
R/W
R/W
X
X
9
1
EEAR8
EEAR0
R/W
R/W
ATmega128
8
0
X
X
Figure
EEARH
EEARL
See “Prevent-
10.
21
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