ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 31

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

XMEM Register
Description
MCU Control Register
– MCUCR
External Memory
Control Register A –
XMCRA
2467S–AVR–07/09
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1
Note:
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
• Bit 6 – SRW10: Wait-state Select Bit
For a detailed description in non-ATmega103 compatibility mode, see common description for
the SRWn bits below (XMCRA description). In ATmega103 compatibility mode, writing SRW10
to one enables the wait-state and one extra cycle is added during read/write strobe as shown in
Figure
• Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write
this bit to zero for compatibility with future devices.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
14.
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
DA7:0
A15:8
CPU
ALE
WR
RD
SRE
R/W
)
R
7
0
7
–
0
Prev. addr.
Prev. data
Prev. data
Prev. data
SRW10
SRL2
R/W
R/W
T1
6
0
6
0
Address
Address
SRL1
R/W
R/W
SE
Address
5
0
5
0
T2
XX
SRL0
SM1
R/W
R/W
4
0
4
0
Address
T3
Data
Data
Data
SRW01
SM0
R/W
R/W
3
0
3
0
T4
SRW00
SM2
R/W
R/W
2
0
2
0
T5
SRW11
IVSEL
R/W
R/W
1
0
1
0
IVCE
T6
R/W
ATmega128
R
0
0
0
–
0
(1)
MCUCR
XMCRA
T7
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