ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 147

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Definitions
Timer/Counter
Clock Sources
Counter Unit
2467S–AVR–07/09
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC2).
Unit” on page 148.
which can be used to generate an output compare interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2
counter value and so on).
The definitions in
Table 63. Definitions
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the clock select logic which is controlled by the clock select (CS22:0) bits located
in the Timer/Counter Control Register (TCCR2). For details on clock sources and prescaler, see
“Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
62
Figure 62. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
count
direction
clear
clk
top
shows a block diagram of the counter and its surroundings.
Tn
DATA BUS
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The
assignment is dependent on the mode of operation.
TCNTn
Increment or decrement TCNT2 by 1.
Select between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT2 has reached maximum value.
Table 63
for details. The compare match event will also set the compare flag (OCF2)
are also used extensively throughout the document.
direction
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
T0
Tn
in the following.
( From Prescaler )
Clock Select
Detector
Edge
ATmega128
See “Output Compare
144.
Tn
Figure
147