ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 301

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

SPI Serial
Programming
Algorithm
2467S–AVR–07/09
Figure 144. SPI Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruc-
tion. The Chip Erase operation turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
High:> 2 CPU clock cycles for f
When writing serial data to the ATmega128, data is clocked on the rising edge of SCK.
When reading data from the ATmega128, data is clocked on the falling edge of SCK. See
145
To program and verify the ATmega128 in the SPI Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
As an alternative to using the RESET signal, PEN can be held low during Power-on
Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is
important. If the programmer cannot guarantee that SCK is held low during power-up, the
PEN method cannot be used. The device must be powered down in order to commence
normal operation when using this method.
Enable serial instruction to pin MOSI.
for timing details.
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
2. V
XTAL1 pin.
CC
- 0.3V < AVCC < V
PDO
SCK
PDI
CC
ck
and GND while RESET and SCK are set to “0”. In some sys-
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 2.7 - 5.5V.
PE0
PE1
PB1
XTAL1
RESET
GND
(1)
AVCC
VCC
+2.7 - 5.5V
+2.7 - 5.5V
Table
ck
ck
145):
(2)
12 MHz
12 MHz
ATmega128
Figure
301