ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 60

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

SICR12
SICR13
SICR14
SICR15
SICR10
SICR11
SICR8
SICR9
External Read/Write Address: 110
Reset Value: 0000
15 - 9
Bit
8
7
6
5
15
0
0
0
0
0
0
0
0
H
STIN#QEN3
STIN#QEN2
STIN#QEN1
STIN#QEN0
14
0
0
0
0
0
0
0
0
Unused
Name
Table 26 - Stream Input Control Register 8 to 15 (SICR8 to SICR15)
13
0
0
0
0
0
0
0
0
H
,
12
0
0
0
0
0
0
0
0
112
H
Reserved. In normal functional mode, these bits MUST be set to zero.
Quadrant Frame 3 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch24 to
31, Ch48 to 63 and Ch96 to 127 for the 2.048 Mbps, 4.096 Mbps and
8.192 Mbps mode respectively.
Quadrant Frame 2 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch16 to
23, Ch32 to 47 and Ch64 to 95 for the 2.048 Mbps, 4.096 Mbps and
8.192 Mbps mode respectively.
Quadrant Frame 1 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch8 to 15,
Ch16 to 31 and Ch32 to 63 for the 2.048 Mbps, 4.096 Mbps and 8.192 Mbps
mode respectively.
Quadrant Frame 0 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7,
Ch0 to 15 and Ch0 to 31 for 2.048 Mbps, the 4.096 Mbps and 8.192 Mbps
mode respectively.
,
11
114
0
0
0
0
0
0
0
0
H
,
116
10
0
0
0
0
0
0
0
0
H
Zarlink Semiconductor Inc.
,
118
9
0
0
0
0
0
0
0
0
ZL50010
H
,
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
60
STIN8
QEN3
STIN9
QEN3
QEN3
QEN3
QEN3
QEN3
QEN3
QEN3
11A
8
H
,
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
11C
STIN8
QEN2
STIN9
QEN2
QEN2
QEN2
QEN2
QEN2
QEN2
QEN2
7
H
,
Description
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
STIN8
QEN1
STIN9
QEN1
QEN1
QEN1
QEN1
QEN1
QEN1
QEN1
11E
6
H
,
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
STIN8
STIN9
QEN0
QEN0
QEN0
QEN0
QEN0
QEN0
QEN0
QEN0
5
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
STIN8
STIN9
SMP1
SMP1
SMP1
SMP1
SMP1
SMP1
SMP1
SMP1
4
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
STIN8
STIN9
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
3
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
STIN8
STIN9
DR2
DR2
DR2
DR2
DR2
DR2
DR2
DR2
2
Data Sheet
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
STIN8
STIN9
DR1
DR1
DR1
DR1
DR1
DR1
DR1
DR1
1
STIN10
STIN11
STIN12
STIN13
STIN14
STIN15
STIN8
STIN9
DR0
DR0
DR0
DR0
DR0
DR0
DR0
DR0
0