ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 35

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.10
Figure 25 shows the functional block diagram of the DPLL. Major functional blocks are described in the following
sections. When the DPLL is in Master or Freerun mode, the APLL input is C20i from the oscillator and the APLL
multiplies C20i to generate the DPLL master clock MCKDPLL.
2.10.1
The ST-BUS input frame pulse (FPi) is sampled with the ST-BUS input clock (CKi) inside the CKi/FPi synchronizer
to create the 8 kHz reference CKi/FPi. Either CKi/FPi or PRI_REF is selected by the reference select bit
(P_REFSEL in the DOM register) as the PRI_REF_INT input to the Reference Select Mux in Figure 25.
CKi
PRI_REF
FPi
(P_REFSEL bit in DOM)
C20i
(Selected by FP0-1 bits in DOM)
(Selected by FS0-1 bits in DOM)
CKi/FPi
Synchronizer
DPLL Functional Description
P_REFSEL
CKi/FPi Synchronizer and PRI_REF Select Mux Circuits
(SKC0-2 bits in DPOA)
(REFSEL bit in DOM)
(MRST bit in DOM)
SKEW_CONTROL
FREQ_MOD_SEC
FREQ_MOD_PRI
APLL
FORCED_SEC
AUTODETECT
FORCED_PRI
MTIE_RESET
REF_SELX
SEC_REF
PRI_REF
Select
MUX
MCKDPLL
PRI_REF_INT
Reference
Reference
Frequency
Figure 25 - DPLL Functional Block Diagram
Monitor
Monitor
Mode
Reference
MUX
Select
MUX
Zarlink Semiconductor Inc.
ZL50010
Control
LOS
35
REF
REF_SEL
LOS_PRI
LOS_SEC
REF_SELECT
FREQ_MOD
(Fig. 25)
Control
Skew
(FREERUN bit in DOM)
(POS0-6 bits in DPOA)
Machine
(Fig. 26)
State
REF_IN
PHASE_OFFSET
RESET Pin
FREERUN
MTIE
MTIE_START
HOLDOVER
FEEDBACK
REF_VIR
(Fig 27)
PLL
Data Sheet
FRAME
MCKTDM