ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 32

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The DPLL intrinsic jitter is 6.25 ns peak to peak. In Master and Freerun modes, the DPLL intrinsic jitter will be
added onto the ST-BUS outputs. In Bypass mode, the DPLL is completely bypassed and the DPLL intrinsic jitter will
not be added to the ST-BUS outputs.
2.9.1
DPLL Master mode is selected by the setting shown in Table 14. Asserting the RESET pin low will also put the
DPLL into Master mode since RESET clears all the registers. In Master mode, the DPLL generates the MCKTDM
clock synchronized to one of 3 timing reference signals. It provides jitter attenuation and holdover functions, and
automatic reference switching between two of the timing references. MCKTDM provides timing for the TDM
switching function and for the ST-BUS outputs. Hence the Master mode ST-BUS output clocks and frame pulses
are synchronized to the reference and can be used to provide a system’s ST-BUS timing.
2.9.1.1
The DPLL has access to two independent external references at the PRI_REF and SEC_REF input pins. Typically
PRI_REF and SEC_REF are from the network. Additionally an internal 8 kHz signal (CKi/FPi) derived from the CKi
and FPi inputs can be selected to replace PRI_REF. The reference chosen from between PRI_REF and CKi/FPi is
called the primary reference. SEC_REF is known as the secondary reference. The P_REFSEL bit of the DOM
register is used to select between PRI_REF and CKi/FPi as the primary reference.
Either the primary reference (selected from between PRI_REF and CKi/FPi) or the secondary reference
(SEC_REF) can be designated as the "preferred" reference via the REFSEL bit of the DOM register. The remaining
reference becomes the "backup" reference. For example, if SEC_REF is the preferred reference, then the backup
reference is the primary reference selected from between PRI_REF and CKi/FPi. The preferred and backup
references are used in automatic reference switching.
The PRI_REF and SEC_REF inputs do not have to be at the same nominal frequency. Each can be independently
programmed to be either 8 kHz, 1.544 MHz or 2.408 MHz via the FP1-0 and FS1-0 bits of the DOM register. When
the internal 8 kHz signal CKi/FPi is selected as the primary reference instead of PRI_REF, the FP1-0 bits must be
set to 00.
The DPLL operates on the rising edge of the selected reference. The polarity of the PRI_REF and SEC_REF inputs
can be inverted via the PINV and SINV bits of the DOM register.
DPLL Master Mode
Master Mode Reference Inputs
Bit 14 of CR
0
0
1
Table 14 - DPLL Operating Mode Settings
Zarlink Semiconductor Inc.
Bit 0 of DOM
ZL50010
1 or 0
0
1
32
Freerun mode
Bypass mode
Master mode
Mode
Data Sheet