ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 38

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.10.7
The MTIE circuit prevents any significant change in the DPLL output clock phase during a reference switch. The
input references can have any relationship between their phases. The DPLL output follows the selected input
reference. Thus a switch from one reference to another could cause a large phase jump in the DPLL output if the
MTIE circuit did not exist. The phase jump would be transferred to the ST-BUS outputs. The MTIE circuit works to
preserve the continuity of the DPLL output so that it appears no reference switch had occurred.
The MTIE circuit receives the skewed reference from the Skew Control circuit and delays it. This delayed signal is
used as a virtual reference (REF_VIR in Figure 25 on page 35) to input to the PLL block. Therefore the virtual
reference is a delayed version of the selected reference. During a reference switch, the state machine first changes
the operation of the PLL from normal to holdover. In holdover, the PLL no longer uses the virtual reference signal,
but generates a stable output clock using stored values. When the state machine changes to MTIE PRI or MTIE
SEC, the PLL block remains operating in holdover. The MTIE circuit measures the phase delay between the current
phase (FEEDBACK signal in Figure 25 on page 35) and the phase of the new reference signal (REF_IN in Figure
25). The MTIE circuit stores the measured delay. From now on the MTIE circuit always delays the reference signal
by the stored value to become the virtual reference. The virtual reference is now at the same phase position it
would have been if the reference switch had not taken place. The state machine then returns the PLL to normal
operation.
The PLL now uses the new virtual reference signal. Since no phase step took place at the input of the PLL, no
phase step occurs at the PLL output. In other words, reference switching will not cause a phase change at the PLL
block input, or at the PLL output.
During the measurement process, the new reference is sampled asynchronously with an internal clock. Thus the
delay between the new reference and the old virtual reference has a small measurement error. This measurement
error will cause a small phase change (Time Interval Error) at the PLL output. Even if there is no phase difference
between the primary and secondary references, each time a reference switch is made the delay (phase offset)
between the DPLL input and output will change. The value of the delay is the sum of the measurement errors from
all the reference switches. After many switches, the delay between the selected input reference and the DPLL
output can become unacceptably large. The user should provide MTIE reset (via MRST bit in the DOM register) to
realign the output clock to the nearest edge of the selected input reference. After the realignment, the phase offset
between the input reference and DPLL output is the amount programmed into the DPOA register POS6-0 and
SKC2-0 bits.
2.10.8
As shown in Figure 28, the PLL circuit consists of a Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop
Filter, Digitally Controlled Oscillator, Divider and Frequency Select Mux.
PHASE_OFFSET
REF
FREQ_MOD
HOLDOVER
FREERUN
Maximum Time Interval Error (MTIE) Circuit
Phase-Locked Loop (PLL) Circuit
Detector
Phase
FEEDBACK
Figure 28 - Block Diagram of the PLL Module
Phase
Offset
Adder
Zarlink Semiconductor Inc.
Limiter
Phase
Slope
ZL50010
38
Filter
Loop
Frequency
Select
DCO
MUX
Divider
C1M5
C2M
Data Sheet
MCKTDM
FRAME