ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 56

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4 - 3
External Read/Write Address: 030
Bit
Reset Value: 0000
15
0
2
1
0
14
0
P_REFSEL
FREERUN
FP1 - FP0
REFSEL
Name
13
0
H
Table 22 - DPLL Operation Mode (DOM) Register Bits (continued)
12
0
PRI_REF Frequency Selection Bits: These bits are used to specify the nominal
clock frequency of the PRI_REF input.
When the P_REFSEL bit is high to select the internal 8 kHz signal (derived from the
FPi and CKi inputs) as primary reference, these bits must be set to 00.
Preferred Reference Selection Bit: When this bit is low, the preferred reference is
the primary reference selected via the P_REFSEL bit (PRI_REF or internal 8 kHz from
FPi and CKi). When this bit is high, the preferred reference is the secondary reference
(SEC_REF).
Primary Reference Source Selection Bit: This bit is used to select the primary
reference input to the DPLL from between 2 sources. When this bit is low, the primary
reference is from the PRI_REF pin. When this bit is high, the primary reference is from
the internal 8 kHz generated from the FPi and CKi inputs. When this bit is high, the
FP1-0 bits must be set to 00.
If the internal 8 kHz signal is selected as the primary reference, the user must ensure
that the FPi and CKi input signals will be re-applied after the internal 8 kHz signal is
lost (or failed). If FPi or CKi is not presented to the device, the device cannot accept
STi0-15 input data.
Freerun Control Bit: When this bit is low and bit 14 of the Control Register is low, the
DPLL is in Master mode. When this bit is high and bit 14 of the Control Register is low,
the DPLL is in Freerun mode. This bit has no effect when bit 14 of the Control Register
is high.
MRST
11
H
FDM1
10
FDM0
FP1
9
0
0
1
1
Zarlink Semiconductor Inc.
SINV
ZL50010
8
FP0
0
1
0
1
56
PINV
7
8 kHz (PRI_REF or CKi/FPi)
Description
FS1
6
Primary Reference
1.544 MHz
2.048 MHz
FS0
Reserved
5
FP1
4
FP0
3
REF
SEL
2
P_REF
SEL
1
Data Sheet
FREE
RUN
0