ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 17

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.1.3
When the negative input frame pulse and negative input clock formats are used, the input frame boundary is
defined by the falling edge of the CKi input clock while the FPi is low. When the input data rate is 2.048 Mbps,
4.096 Mbps or 8.192 Mbps, there are 32, 64 or 128 channels per every ST-BUS frame respectively. Figure 7 shows
the details:
(16.384 MHz)
(4.096 Mbps)
(8.192 Mbps)
(2.048 Mbps)
(4.096 MHz)
(8.192 MHz)
Input Frame Boundary
ST-BUS Input Timing
(8 kHz)
CKi
CKi
CKi
FPi
FPi
FPi
STi
STi
STi
3
1
2
0
1 0
Figure 7 - ST-BUS Input Timing for Various Input Data Rates
0
7
7
6
7
5
Channel 0
6
4
3
5
2
6
Channel 0
1 0
4
7
Zarlink Semiconductor Inc.
3
6
5
5
Channel 1
Channel 0
ZL50010
2
4
3
1
17
2
4
1 0
0
6
3
5
Channel 126
6
4
Channel 31
3
5
2
Input Frame Boundary
2
Channel 63
1 0
4
7
3
6
1
5
Channel 127
2
4
3
1
2
0
1 0
0
Data Sheet
7 6
7
7