ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 39

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Phase Detector - The Phase Detector compares the virtual reference signal from the MTIE circuit (REF_VIR) with
the FEEDBACK signal from the Frequency Select Mux. It provides an error signal corresponding to the phase
difference between the signals’ rising edges. This error signal is passed to the Phase Offset Adder.
Phase Offset Adder - The Phase Offset Adder adds the PHASE_OFFSET word (POS6-0 bits of the DPOA register)
to the error signal from the Phase Detector to create the final phase error. This value is passed to the Phase Slope
Limiter. The phase offset word (POS6-0) can be positive or negative. Since the PLL will stabilize to a situation
where the average Phase Offset Adder output is zero, a non-zero phase offset word will result in a static phase
offset between the input and output of the DPLL.
The phase offset word is a 7-bit 2’s complement value. If the selected input reference is 8 kHz or 2.048 MHz, the
step size of the static phase offset is 15.2 ns. The static phase offset can be set between -0.96 µs and +0.97 µs. If
the selected input reference is 1.544 MHz, the step size is 20.2 ns and the static phase offset can be set between -
1.27 µs and +1.29 µs.
The resolution of the Skew Control circuit is 1.9 ns. Its effect is additional to that of the phase offset word. Thus
using the Skew Control bits (SKC2-0 of the DPOA register) together with the phase offset word, users can set a
total static phase offset between -0.96 µs and +0.99 µs if the selected input reference is either 8 kHz or 2.048 MHz.
If the selected reference is 1.544 MHz, the total static phase offset can be between -1.27 µs and +1.30 µs.
Phase Slope Limiter - The Phase Slope Limiter receives the error signal from the Phase Offset Adder and ensures
that the DPLL output responds to all input transient conditions with an output phase slope below a preset limit. The
limit is based upon telecom standards requirements.
Loop Filter - The Loop Filter is similar to a first order low pass filter with a 1.52 Hz cutoff frequency for all 3
reference frequency selections (8 kHz, 1.544 MHz or 2.048 MHz). This filter defines the jitter transfer characteristic
of the DPLL.
Digitally Controlled Oscillator (DCO) - The DCO generates a high speed digital clock output. The DCO’s frequency
is modulated by the frequency offset value from the Loop Filter. The DCO output is the MCKTDM clock in
Figure 25 on page 35 and Figure 28 on page 38. MCKTDM provides timing for the TDM switching function, and
timing for the ST-BUS outputs.
When the State Machine is in the Normal state, the DCO accepts the offset frequency value which represents the
limited and filtered phase error between the input reference and the DCO feedback signal. Based on the offset
value the DCO generates an output clock which is synchronized to the selected input reference.
When the State Machine is in the Holdover state, the DCO uses a frequency offset value which has been stored
32 ms to 64 ms prior to exiting from the Normal state. Thus the DCO is running at the same frequency it was
previously running at when the State Machine was in the Normal state.
When the DPLL is in Freerun mode, the frequency offset is ignored and the DCO is free running at its preset center
frequency.
Divider - The Divider divides down the DCO output frequency. The following signals are generated:
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One of these signals is selected as the PLL feedback reference signal by the Frequency Select Mux circuit. The
clocks have 50% nominal duty cycle. FRAME is a 122 ns wide negative frame pulse. The duty cycle of the clocks
are not affected by the crystal oscillator duty cycle. Since these signals are generated from a common signal inside
the DPLL, the frame pulse and clock outputs are always locked to one another. They are also locked to the selected
input reference when the DPLL is in lock.
Frequency Select Mux - According to the selected input reference of the DPLL, this multiplexer will select the
appropriate divider output C2M, C1M5 or FRAME as the feedback signal to the PLL and MTIE circuits.
C2M (a 2.048 MHz clock)
C1M5 (a 1.544 MHz clock)
FRAME (an 8 kHz frame pulse)
Zarlink Semiconductor Inc.
ZL50010
39
Data Sheet