ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 15

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.0
The device uses the ST-BUS input frame pulse and the ST-BUS input clock to define the input frame boundary and
timing for the ST-BUS input streams with various data rates (2.048 Mbps, 4.096 Mbps and/or 8.192 Mbps). The
output frame boundary is defined by the output frame pulses and the output clock timing for the ST-BUS output
streams with various data rates (2.048 Mbps, 4.096 Mbps and/or 8.192 Mbps).
By using Zarlink’s message mode capability, microprocessor data can be broadcast to the data output streams on a
per channel basis. This feature is useful for transferring control and status information for external circuits or other
ST-BUS devices.
The on-chip DPLL can be operated in one of three modes: Master, Freerun or Bypass. In Master mode, the DPLL
can be used as a system’s timing source to provide ST-BUS clocks and frame pulses which are synchronized to the
network. In Freerun mode, the DPLL can be used to provide system ST-BUS timing which is independent of the
network. In Bypass mode, the DPLL is completely bypassed and the device operates entirely from system timing
provided by the input ST-BUS clock and frame pulse. An external 20.000 MHz crystal or clock oscillator is required
in Master and Freerun modes. The DPLL intrinsic jitter is 6.25 ns peak to peak.
In Master mode, the DPLL is synchronized to either the PRI_REF input, the SEC_REF input, or to an internal 8 kHz
signal derived from the input ST-BUS clock and frame pulse. The PRI_REF and SEC_REF inputs accept 8 kHz,
1.544 MHz or 2.048 MHz network timing reference signals. The DPLL also provides reference monitoring,
automatic bit-error-free reference switching, jitter attenuation and holdover functions. The DPLL output is an
internal high speed clock from which output ST-BUS clock and frame pulses are generated.
A non-multiplexed microprocessor port allows users to program the device with various operating modes and
switching configurations. Users can use the microprocessor port to perform register read/write, connection memory
read/write and data memory read operations. The microprocessor port has a 12 bit address bus, a 16 bit data bus
and four control signals.
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
2.0
A functional block diagram of the ZL50010 is shown in Figure 1 on page 1.
2.1
The device has 16 ST-BUS serial data inputs. Any of the 16 inputs can be programmed to accept different data
rates, 2.048 Mbps, 4.096 Mbps or 8.192 Mbps.
2.1.1
Any ST-BUS input can be programmed to accept the 2.048 Mbps, 4.096 Mbps or 8.192 Mbps data using Bit 0 to 2
in the stream input control registers, SICR0 to SICR15 as shown in Table 25 on page 58 and Table 26 on page 60.
The maximum number of input channels is 512 channels. External pull-up or pull-down resistors are required for
any unused ST-BUS inputs.
2.1.2
The frame pulse input FPi accepts the frame pulse used for the highest input data rate. The frame pulse is an
8 kHz input signal which stays low for 244 ns, 122 ns or 61 ns for the input data rate of 2.048 Mbps, 4.096 Mbps or
8.192 Mbps respectively. The frequency of CKi must be twice the highest data rate. For example, if users present
the ZL50010 with 2.048 Mbps and 8.192 Mbps input data, the device should be programmed to accept the input
clock of 16.384 MHz and the frame pulse which stays low for 61 ns.
ST-BUS Input Data Rate and Input Timing
Device Overview
Functional Description
ST-BUS Input Operation Mode
Frame Pulse Input and Clock Input Timing
Zarlink Semiconductor Inc.
ZL50010
15
Data Sheet