ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 11

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
LQFP Pin
Number
24 - 28
14, 15
12
13
16
17
19
20
22
30
31
A6, A5, B6,
LBGA Ball
Number
C9, C8
B5, C7
C10
D8
C4
A9
B8
A8
A7
B7
A4
NC1, NC2
CLKBYPS
SEC_REF
V
PRI_REF
V
Name
DD_APLL
XTALo
IC0 - 4
XTALi
ss_APLL
TM1
TM2
Zarlink Semiconductor Inc.
APLL Test Pin 1: For normal operation, this input MUST be
low.
APLL Test Pin 2: For normal operation, this input MUST be
low.
No Connection: These pins MUST be left unconnected.
Ground for the APLL Circuit.
Power Supply for the on-chip Analog Phase-Locked Loop
(APLL) Circuit: +3.3 V
Oscillator Clock Output (3.3 V Output). This pin is connected
to a 20 MHz crystal (see Figure 31 on page 44), or it is left
unconnected if a clock oscillator is connected to the XTALi pin
(see Figure 32 on page 45). If the device is to be used in DPLL
Bypass mode only, the crystal or clock oscillator can be
omitted, in which case this pin must be left unconnected.
Oscillator Clock Input (3.3 V Input). This pin is connected to
a 20 MHz crystal (see Figure 31 on page 44), or it is connected
to a clock oscillator (see Figure 32 on page 45). If the device is
to be used in DPLL Bypass mode only, the crystal or clock
oscillator can be omitted, in which case this pin must be held
low.
Test Clock Input: For device testing only, in normal operation,
this input MUST be low.
Internal connection (3.3 V Tolerant Inputs with internal
pull-down):
In normal mode, these pins must be low.
Primary Reference Input (5 V Tolerant Input): This pin
accepts an 8 kHz, 1.544 MHz or 2.048 MHz timing reference. It
is used as one of the primary references for the DPLL in the
Master mode. This pin is ignored in the DPLL Freerun or
Bypass Mode.
When this pin is not in use, it is required to be driven high or
low by connecting it to Vdd or ground through an external pull-
up resistor or external pull-down resistor.
Secondary Reference Input (5 V Tolerant Inputs): This pins
accept an 8 kHz, 1.544 MHz or 2.048 MHz timing reference. It
is used as the secondary reference for the DPLL in the Master
mode. This pin is ignored in the DPLL Freerun or Bypass
Mode.
When this pin is not in use, it is required to be driven high or
low by connecting it to Vdd ground, through an external pull-up
resistor or external pull-down resistor.
ZL50010
11
Description
Data Sheet